Consider adding SystemVerilog support by collaborating with Verible + Surelog

[mithro]

SystemVerilog is a very popular hardware description language (HDL). Google is working on improving the ecosystem around this language, including developing linting and code fixing tooling. It would be awesome for SystemVerilog to be supported via coala.

The two primary projects are;

• https://github.com/google/verible (Yacc + Bison based)

  The Verible project's main mission is to parse SystemVerilog (IEEE 1800-2017) (as standardized in the SV-LRM) for a wide variety of applications, including developer tools.

• https://github.com/alainmarcel/Surelog (ANTLR based)

  SystemVerilog 2017 Pre-processor, Parser, UHDM Compiler. Provides IEEE Design/TB VPI and Python AST API.

  Goal

  This project aims at providing a complete SystemVerilog 2017 front-end: a preprocessor, a parser, an elaborator for both design and testbench.

  Applications

  Linter, Simulator, Synthesis tool, Formal tools can use this front-end. They either can be developed as plugins (linked with) or use this front-end as an intermediate step of their compilation flows using the on-disk serialized models (UHDM).

We are also collaborating with the https://github.com/hdl organization to provide package of the tools via both containers and through conda. We are also looking at doing something similar to https://yowasp.github.io/ (which distributes WASM binaries through PyPi) in the future.

[svenka3]

@mithro I share this interest with you :-) As a start I see Verilator Lint being supported. I would certainly like to add more. Let's pick this thread up and support SV with various linters out there!

Thanks